1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor read-only memory (ROM) and a method of manufacture thereof. The present invention further provides a method of directly transforming CMOS-compatible single-poly one-time programming (OTP) memory into coded non-volatile memory without the need for redesigning the peripheral circuitry.
2. Description of the Prior Art
In the strictest sense, read-only memory (ROM), as its name implies, is a data storage medium that cannot be written to (or erased), but only read from. Today, ROM may even refer more broadly to any data storage medium that is not randomly accessible. In most modern applications ROM is utilized for storage of program code that should not be changed frequently, or for storage of data, such as music, video, or other files that may be written once and read many times. In practice, ROM may be programmed with data during fabrication, or may be written to electronically. Thus, ROM technology may be roughly divided into mask-programmable ROM (MPROM) and electrically-programmable ROM (EPROM).
MPROM technologies may be further take form in at least three categories, including diffusion ROM, VTH ROM, and via ROM. Please refer to FIG. 1, which is a diagram of eight ROM bits defined through active area (AA) regions or lack thereof. As shown in FIG. 1, polysilicon may be utilized to form word lines W0-W3, and a metal layer may be utilized to form bit lines B0-B1 over diffusion regions. Contacts C0-C3 may be formed to electrically connect the bit lines B0-B1 with the diffusion regions. During fabrication, diffusion may be allowed or blocked through use of a mask. Thus, by defining block regions BR0-BR2 in the mask, diffusion may be prevented at intersections I02, I10, I12 corresponding to the bit line BL0 and the word line WL2, the bit line BL1 and the word line WL0, and the bit line BL1 and the word line WL2, respectively. As shown in FIG. 1, two diffusion regions DR0, DR1 are formed in the substrate due to use of the block regions BR0-BR2. In the example shown in FIG. 1, bit polarity of transistors formed at intersections I00, I01, I03, I11, I13 is “1”, whereas bit polarity at the intersections I02, I10, I12 is “0”, as no transistors are formed.
Please refer to FIG. 2, which is a diagram of eight ROM bits defined through high/low VTH transistors. Similar to FIG. 1, polysilicon may be utilized to form word lines W0-W3, and a metal layer may be utilized to form bit lines B0-B1 over a diffusion region DR. Contacts C0-C3 may be formed to electrically connect the bitlines B0-B1 with the diffusion region DR. During fabrication, definition of high VTH transistors may be accomplished through use of an extra mask. Thus, by defining high VTH regions HVR0-HVR2 in the mask, transistors at intersections I02, I10, I12 corresponding to the bit line BL0 and the word line WL2, the bit line BL1 and the word line WL0, and the bit line BL1 and the word line WL2, respectively, may have relatively high threshold voltage (VTH). In the example shown in FIG. 2, bit polarity of transistors formed at intersections I00, I01, I03, I11, I13 is “1”, whereas bit polarity at the intersections I02, I10, I12 is “0”.
Please refer to FIG. 3, which is a diagram of eight ROM bits defined through use of vias (contacts) Similar to FIG. 1, polysilicon may be utilized to form word lines W0-W3, and a metal layer may be utilized to form bit lines B0-B1 over diffusion regions DR0, DR1, DR3. Contacts C0-C4 may be formed to electrically connect the bit lines B0-B1 with the diffusion regions DR0, DR1, DR3. During fabrication, ROM code maybe defined through use of the contacts C0-C4. Thus, by placing contacts C0-C4, transistors are formed at intersections I00, I01, I03, I11, I13 corresponding to the bit line BL0 and the word lines WL0, WL1, WL3, and to the bit line BL1 and the word lines WL1, WL3, respectively. In the example shown in FIG. 3, bit polarity of transistors formed at intersections I00, I01, I03, I11, I13 is “1”, whereas bit polarity at the intersections I02, I10, I12 is “0”.
Please refer to FIG. 4A and FIG. 4B, which are diagrams of an EPROM bit. FIG. 4A shows a top view of layout of the EPROM bit; FIG. 4B shows a cutaway view of the EPROM bit along line A-A of FIG. 4A. The EPROM bit comprises a bit line BL0, a word line WL0, a first contact C0, an a second contact C1. The first contact C0 is formed on a first diffusion region DR0; the second contact C1 is formed on a third diffusion region DR2. The word line WL0 may be formed of polysilicon, and the bit line BL0 may be formed of metal electrically connected to the first diffusion region DR0 and the third diffusion region DR2 through the first contact C0 and the second contact C1, respectively. The EPROM bit further comprises a floating polysilicon layer FPL0 utilized for programming the EPROM bit. As shown in FIG. 4B, the EPROM bit may be programmed by introducing charges into the floating polysilicon layer FPL0. Thus, channel formation may be induced between a second diffusion region DR1 and the third diffusion region DR2. If no charges are introduced into the floating polysilicon layer FPL0, no channel formation is induced between the second diffusion region DR1 and the third diffusion region DR2. In this way, distinction may be made between “1” and “0” polarities at each EPROM bit.
Please refer to FIG. 5A and FIG. 5B, which are diagrams of a second type of EPROM bit. FIG. 5A shows a top view of layout of the EPROM bit; FIG. 5B shows a cutaway view of the EPROM bit along line B-B of FIG. 5A. Similar to the EPROM bit shown in FIG. 4A and FIG. 4B, the EPROM bit of FIG. 5A and FIG. 5B includes a bit line BL0, a word line WL0, a first contact C0, an a second contact Cl. The first contact C0 is formed on a first diffusion region DR0; the second contact C1 is formed on a third diffusion region DR2. The word line WL0 may be formed of polysilicon, and the bit line BL0 may be formed of metal electrically connected to the first diffusion region DR0 and the third diffusion region DR2 through the first contact C0 and the second contact C1, respectively. Unlike the EPROM bit of FIG. 4A and FIG. 4B, the EPROM bit of FIG. 5A and FIG. 5B includes an ONO (oxide-nitride-oxide) dielectric layer ONO0 between a polysilicon layer PL0 and a substrate on which the EPROM bit is formed. The ONO dielectric layer ONO0 may act as a charge-trapping layer. Thus, presence or absence of charges in the ONO dielectric layer ONO0 may be utilized for distinguishing bit polarity of the EPROM bit shown in FIG. 5A and FIG. 5B, as charges in the ONO dielectric layer ONO0 induce channel formation between a second diffusion region DR1 and the third diffusion region DR2.
Please refer to FIG. 6A and FIG. 6B, which are diagrams of a third type of EPROM bit typically utilized in flash memory applications. FIG. 6A shows a top view of layout of the EPROM bit; FIG. 6B shows a cutaway view of the EPROM bit along line C-C of FIG. 6A. Similar to the EPROM bit shown in FIG. 5A and FIG. 5B, the EPROM bit of FIG. 6A and FIG. 6B includes an ONO dielectric layer ONO1. However, the ONO dielectric layer ONO1 is formed between a polysilicon layer of the word line WL0 and a polysilicon layer PL0 formed between the word line WL0 and the substrate. Thus, the ONO dielectric layer ONO1 acts as an inter-polysilicon dielectric layer. A first contact C0 is formed on a first diffusion region DR0; a second contact C1 is formed on a second diffusion region DR1. The bit line BL0 may be formed of metal electrically connected to the first diffusion region DR0 and the third diffusion region DR2 through the first contact C0 and the second contact C1, respectively. To program the EPROM bit, charges may be introduced into the polysilicon layer PL0. Thus, bit polarity of the EPROM bit may be distinguished based on induction, or lack thereof, of a channel between the first diffusion region DR0 and the second diffusion region DR1.
The methods described above and shown in FIG. 1, FIG. 2, and FIG. 3 have a number of disadvantages. For example, peripheral circuitry may need to be redesigned, product development may be long and costly, yield is low, and required test time is long. Further, no simple method exists for transforming the EPROM topologies shown in FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, FIG. 6A, and FIG. 6B into mask programmable memory without changing the fabrication process utilized for forming the EPROM bits.